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-- Company: 
-- Engineer:
--
-- Create Date:    21:06:53 08/15/05
-- Design Name:    
-- Module Name:    blinkylights - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity blinkylights is
	port(	an:  out std_logic_vector(3 downto 0);
			led: out std_logic_vector(7 downto 0);
			sw:  in std_logic_vector(7 downto 0);
         mclk: in std_logic
	);
end blinkylights;

architecture Behavioral of blinkylights is
	signal secclk_c: std_logic_vector(23 downto 0);
	signal secclk: std_logic;
	signal ledreg: std_logic_vector(7 downto 0) := "00000001";
begin

	second_clock: process(mclk)
	begin
		if (mclk = '1' and mclk'Event) then
			secclk_c <= secclk_c + 1;
			if (sw(3) = '1') then
				secclk <= secclk_c(23);
			else
				secclk <= secclk_c(20);
			end if;
		end if;
	end process; 

	rotate: process(secclk)
	begin
		if (secclk = '1' and secclk'Event and sw(0) = '1') then
			if (sw(2) = '1') then
				ledreg <= (ledreg(0) & ledreg(7 downto 1));
			else
				ledreg <= (ledreg(6 downto 0) & ledreg(7));
			end if;
		end if;
	end process;
	
	led <= ledreg;
	an <= "1111";
end Behavioral;