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-- Company: 
-- Engineer:
--
-- Create Date:    21:02:43 09/16/05
-- Design Name:    
-- Module Name:    ledcounter - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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-- LED Decoder
-- Convert single 4 bit std_logic_vector to led segments.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity leddcd is
    port ( cntr : in std_logic_vector(3 downto 0);
           seg : out std_logic_vector(6 downto 0));
end leddcd;

architecture Behavioral of leddcd is
begin

	-- Mappings for the S3BOARD LED display.
	seg <="1000000" when cntr = "0000" else
	 		"1111001" when cntr = "0001" else
 			"0100100" when cntr = "0010" else
			"0110000" when cntr = "0011" else
			"0011001" when cntr = "0100" else
			"0010010" when cntr = "0101" else
			"0000010" when cntr = "0110" else
			"1111000" when cntr = "0111" else
			"0000000" when cntr = "1000" else
			"0010000" when cntr = "1001" else
			"0001000" when cntr = "1010" else
			"0000011" when cntr = "1011" else
			"1000110" when cntr = "1100" else
			"0100001" when cntr = "1101" else
			"0000110" when cntr = "1110" else
			"0001110";

end Behavioral;


-- 4 digit LED driver
-- Decode 16 bit std_logic_vector and output 4 led digits.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- use IEEE.NUMERIC_BIT.ALL;

entity leddsp is
	port ( dispin : in std_logic_vector(15 downto 0);
			 mclk : in std_logic ;
			 seg : out std_logic_vector(6 downto 0);
			 an : out std_logic_vector(3 downto 0) );
end leddsp;

architecture Behavioral of leddsp is
	signal dclk_c: std_logic_vector(14 downto 0);
	signal dclk: std_logic;
	signal dgtout: std_logic_vector(3 downto 0) ;
	signal dgtnum: std_logic_vector(1 downto 0) := "00";
begin


	divide_clock: process(mclk)
	begin
		if mclk = '1' and mclk'event then
			dclk_c <= dclk_c + 1;
		end if;
	end process; 

	dclk <= dclk_c(14);

	digit_scan: process(dclk)
		variable digit : integer := 0;
	begin
		if (dclk = '1' and dclk'Event) then
			dgtnum <= dgtnum + 1;
		end if;
	end process;

	-- There has to be a better way to do this.
	dgtout <= dispin(3 downto 0) when dgtnum = "00" else
				 dispin(7 downto 4) when dgtnum = "01" else
				 dispin(11 downto 8) when dgtnum = "10" else
				 dispin(15 downto 12) ;

	led_decoder : entity work.leddcd port map (dgtout, seg) ;

	an <= "1110" when dgtnum = "00" else
	      "1101" when dgtnum = "01" else
			"1011" when dgtnum = "10" else
			"0111" ;

end Behavioral;


-- Counts upward on the led display.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ledcounter is
	port(	btn : in std_logic_vector(3 downto 0);
			mclk: in std_logic ;
			seg : out std_logic_vector(6 downto 0);
			seg_dp : out std_logic ;
			an : out std_logic_vector(3 downto 0)
	);
end ledcounter;

architecture Behavioral of ledcounter is
	signal dispnum: std_logic_vector(15 downto 0) := "0000000000000000";
	-- signal dclk_c: std_logic_vector(23 downto 0);
	signal dclk: std_logic;
	signal divi: integer := 0 ;
	-- signal accel: integer := 1 ;
begin

	counter_display : entity work.leddsp
		port map (dispnum, mclk, seg, an) ;

	seg_dp <= '1';

	divide_clock: process(mclk)
	begin
		if mclk = '1' and mclk'event then
			if divi = 0 then
				dclk <= not dclk ;
			end if;
			divi <= divi + 1 ;
			if divi > 25000000 then
				divi <= 0 ;
			end if ;
		end if;
	end process;

--	speedchg: process(mclk, btn(0), btn(1))
--	begin
--		if mclk = '1' and mclk'event then
--			if btn(0) = '1' and btn(0)'event then
--				accel <= accel + 1;
--			end if;
--			if btn(1) = '1' and btn(1)'event and accel > 1 then
--				accel <= accel - 1; 
--			end if;
--		end if;
--	end process;

	countup: process(dclk)
	begin
		if dclk = '1' and dclk'event then
			dispnum <= dispnum + 1;
		end if;
	end process;

end Behavioral;